(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a design for a static random access memory, (SRAM), cell, featuring two self-aligned contact, (SAC), structures, and featuring a buried contact region, and a butt contact structure, used to connect a load resistor to an active device region.
(2) Description of Prior Art
Static random access memory, (SRAM), cells are usually designed to include six, metal oxide semiconductor field effect transistors, (MOSFET), usually four N channel, and two P channel, MOSFETs, or four N channel MOSFET devices, and two load resistors. The SRAM performance and cost objectives have been successfully addressed by the ability of the semiconductor industry to fabricate SRAM devices, using sub-micron features. The smaller features result in a decrease in performance degrading capacitances and resistances, while also allowing a greater number of smaller SRAM chips, to be obtained from a specific size starting substrate, thus reducing the manufacturing cost of a specific SRAM chip.
In addition to the advent of micro-miniaturization, or the use of sub-micron features, specific processes and structures, used for advanced SRAM devices, have been developed. For example self-aligned contact (SAC), structures have been used for metal or polysilicon contact, to source/drain regions, located in the semiconductor substrate, used for the SRAM device. The SAC structure is designed to overlap gate structures, encapsulated with silicon nitride, thus allowing a minimum space to be allotted for the source/drain region, located between gate structures, thus allowing smaller, higher performing SRAM devices to be realized.
This invention will describe a design of, and a process for, a SRAM cell, featuring four MOSFET devices and two polysilicon load resistors. Featured in this invention will be the use of two, SAC structures, one SAC structure, comprised of a polycide, (metal silicide--polysilicon, used to contact a source region of a pull down transistor, while a second SAC structure, comprised of a metal, is used to contact a source region of a pass gate transistor. The use of two SAC structures, results in an increase in performance, as well as a decrease in area, when compared to counterparts fabricated using only one SAC structure. In addition this invention will also feature the use of a buried contact region, under a polysilicon gate structure, and a butted contact structure, to the polysilicon gate structure, allowing contact of a polysilicon load resistor to the underlying active device region. Prior art, such as Yoo, in U.S. Pat. No. 5,573,980, Wuu, et al, in U.S. Pat. No. 5,545,584, Wuu, et al, in U.S. Pat. No. 5,652,174, and Wuu, et al, in U.S. Pat. No. 5,607,879, show a SAC structure, polysilicon load resistors, and buried contact regions. However none of the prior art, or a combination of the prior art, describe the unique combination of features described in this invention, including one polysilicon SAC structure, one metal SAC structure, and the combination of a buried contact region, and a butted contact, used for communication between a polysilicon load resistor and an underlying active device region.